The present invention relates to the field of integrated circuits; more specifically, it relates to input/output (I/O) driver circuits in integrated circuit chips having a power saving mode.
Power consumption of integrated circuit chips is a critical concern in many applications, for example, in portable devices such as lap-top computers and cell phones. In order to save power, integrated circuits used in power saving applications often include two or more power supplies, the normal chip power supply which may be powered down to save power and a alternative power supply that is powered at all times. However, when integrated circuit chips are in xe2x80x9cpower saving modexe2x80x9d they often still need to communicate with off chip devices.
As the normal chip power supply voltage is powered down, it is necessary that unknown or xe2x80x9cin-betweenxe2x80x9d states not be propagated to off chip devices. Further, when the normal chip power supply is powered back up, it is again necessary that unknown or xe2x80x9cin-betweenxe2x80x9d states not be propagated to off chip devices.
Therefore, the possibility of propagating errors between integrated circuits that may be placed in power saving mode and off chip devices is a problem of significant concern to designers of power saving mode chips.
A first aspect of the present invention is an I/O driver comprising: a circuit adapted to be powered by a first power supply, the circuit adapted to receive a first signal referenced to the voltage of a second power supply and adapted to convert the first signal to a second signal of the same logical value as the first signal and referenced to the voltage of the first power supply, the circuit adapted to maintain the second signal on an output of the I/O driver when the second power supply is powered off.
A second aspect of the present invention is An I/O driver comprising: a first circuit adapted to be powered by a first power supply, the first circuit adapted to receive a first signal referenced to the voltage of a second power supply and adapted to convert the first signal to a second signal of the same logical value as the first signal and referenced to the voltage of the first power supply; the first circuit including a first latching circuit, the first latching circuit adapted to maintain the logical state of the second signal when the second power supply is powered off; a second circuit adapted to be powered by the first power supply, the second circuit adapted to receive a third signal referenced to the voltage of the second power supply and adapted to convert the third signal to a fourth signal of the same logical value as the second signal and referenced to the voltage of the first power supply; the second circuit including a second latching circuit, the second latching circuit adapted to maintain the logical state of the fourth signal when the second power supply is powered off; and a combinational logic circuit adapted to combine the second and fourth signals into a fifth signal to maintain the fifth signal on an output of the I/O driver when the second power supply is powered off.
A third aspect of the present invention is a method of maintaining the output state of an I/O driver when an integrated circuit chip is in a low power mode comprising: providing a circuit adapted to be powered by a first power supply, the circuit adapted to receive a first signal referenced to the voltage of a second power supply and adapted to convert the first signal to a second signal of the same logical value as the first signal and referenced to the voltage of the first power supply, the circuit adapted to maintain the second signal on an output of the I/O driver when the second power supply is powered off.